1. Field of the Invention
The invention relates to controlling system bus timing of an embedded system with programmable delay lines, and more specifically to controlling dynamic random access memory (DRAM) associated timing as well as the timing of devices that include an input that is not synchronous to a system clock with programmable delay lines.
2. Description of the Related Art
Embedded systems are generally specialized computer systems that are part of a larger system or machine. Embedded systems have been implemented in various consumer electronics which include watches, microwave ovens, video cassette recorders, and automobiles. A typical embedded system is preprogrammed to perform a dedicated or narrow range of functions with minimal user intervention. In those embedded systems an operating system and various programs are stored in read only memory (ROM). A typical embedded system includes a processor, memory (such as dynamic random access memory (DRAM)), and related peripherals on a single circuit board.
DRAM addressing has normally been accomplished in two stages. In a typical application an address buffer, within the DRAM, initially reads a row address and then reads a column address. These addresses are multiplexed with the multiplexing being controlled by row address strobe (RAS) and column address strobe (CAS) signals. The RAS signal, when asserted, directs the DRAM to accept the address provided as the row address and interpret it accordingly. The CAS signal, when asserted, directs the DRAM to accept the address provided as the column address and interpret it accordingly. In order for the DRAM to function as designed, the duration of the RAS and CAS signals, as well as the time interval between the signals, must meet the specification of the DRAM that is utilized in the embedded system. External delay lines have been utilized to adjust DRAM related timing.
In a typical embedded system each bank of DRAM has similar timing requirements. In those systems, an engineer who tailors memory timing for maximum efficiency of a DRAM bank maximizes efficiency of a memory subsystem.